This invention relates to a rate converter for digital signals including a phase lock loop.
A rate converter for digital signals is an arrangement responsive to a series of input clock pulses defining first time slots and a series of input digital signals supplied to the arrangement at the respective first time slots for producing a series of output clock pulses defining second time slots including excess time slots and a series of output digital signals at the respective ones of the second time slots less the excess time slots. The input digital signals are representative of information being transmitted. The excess time slots are of a predetermined number in each predetermined period of time, such as in each frame period. The predetermined number may be one. The total number of second time slots in the predetermined period less the excess time slots in the predetermined period are equal in number to the first time slots in the predetermined period. The output digital signals are representative of the information carried by the input digital signals. Therefore, stuffing pulses may be transmitted from the arrangement at the respective excess time slots so that an output signal pulse train produced by the arrangement may become a stuffed pulse train described by V. I. Johannes and R. H. McCullough in IEEE Transactions on Communication Technology, Vol. COM-14, No. 5 (October, 1966), pages 562-568, particularly on page 563, under the title of "Multiplexing of Asynchronous Digital Signals Using Pulse Stuffing with Added-Bit Signaling."
As will later be described in more detail with reference to some of the accompanying drawings, a conventional arrangement of the type specified comprises a memory having a memory capacity greater in number than a predetermined number, a first frequency divider responsive to the input clock pulses for producing write-in pulse trains for use in storing the input digital signals in the memory, and a second frequency divider responsive to a series of input timing pulses for producing read-out pulse trains for use in making the memory produce the output digital signals. The output clock pulses are produced by a voltage controlled oscillator having a free running frequency approximately equal to the total number per unit time (i.e. per frame period) of the second time slots. Responsive to the output clock pulses, a counter, such as a frame counter, produces a series of excess-pulse-position specifying pulses for inhibiting application of the output clock pulses to the second frequency divider. Responsive to a difference in phase between the write-in and read-out pulse trains, phase lock means controls the voltage controlled oscillator to make the oscillator operate so that the phase difference is maintained approximately at zero. The phase lock means thus forms a portion of a phase lock feedback loop for the oscillator.
A rate converter of the type described is used in a digital communication system having a plurality of communication channels, m + n in number where m is greater than n, among which m channels are used as operating or live channels, while no channels are preserved as stand-by channels, in order to raise the availability of the m + n channels as a whole. The communication system comprises channel monitoring facilities, as called herein, for incessantly monitoring performance of each live channel and automatic switching devices operatively coupled to the monitoring facilities for switching a live channel to a stand-by as soon as the performance of the live channel is either degraded by a trouble or is otherwise adversely affected. The monitoring facilities comprise rate converters of the type described hereinabove in a transmission terminal station or on the transmitter side of a repeater station. Each rate converter is accompanied by means for placing pilot pulses or parity check bit pulses at the above-mentioned excess time slots to insert such stuffing pulses into the train of output digital signals. In a reception terminal station or on the receiver side of a repeater station, the monitoring facilities comprise means for detecting and stuffing pulses to determine the rate of code errors of each live and stand-by channel.
At an instant at which the performance of a live channel is found to be unsatisfactory, the live channel is switched to a stand-by one. A rate converter for the stand-by channel is supplied with the input clock pulses and input digital signals anew from the instant of changeover. The voltage controlled oscillator for the stand-by channel, which was operating up to the aforesaid instant at the free running frequency, is controlled by the phase lock means so that the phase of the output clock pulses series may be locked or pulled in to the phase of the input clock pulse series. It is, however, to be noted that the phase relation between the write-in and read-out pulses varies during the process of pull-in to frequently step out of a predetermined range of the phase relation. In this event, the digital signals stored in the memory by the write-in pulses are erroneously produced therefrom as the output digital signals by the read-out pulses to undesirably introduce code errors into the output signal pulse train. It is therefore necessary that pull-in be accomplished in the shortest possible period of time.
It should also be noted in conjunction with the above that each repeater station comprises a clock pulse regenerator having a phase lock loop. When the frequency or phase of the output clock pulse series produced by a rate converter of a preceding station rapidly varies due to quick response of the converter to the new input clock pulse series, the phase lock loop of the clock pulse regenerator can not follow the rapid variation to again undesirably introduce a large phase error into the regenerated clock pulse series and accordingly introduces code errors into the digital signal series transmitted from the repeater station either to another repeater station or to a reception terminal station. Particularly when the phase of the output clock pulse series is subjected to a large variation due to stepping-out of the phase relation from the predetermined range to another range where the phase lock loop of the rate converter carries out positive feedback, a large phase error is introduced into the regenerated clock pulse series. On the other hand, it is generally necessary in a communication system having a considerable number of successive repeater stations to avoid excessive accumulation of jitter in timing and consequently to render the noise bandwidth of the system narrow and the damping coefficient of the clock pulse regenerator phase lock loops large by providing the phase lock loops with a slow response to transients. As a result, the rate converter phase lock loop must also have a sufficiently slow response to transients. This requisite is contradictory to the requirements for the quick pull-in.